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high voltage, latch-up proof, 4-channel multiplexer adg5204 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features latch-up proof 3 pf off source capacitance 26 pf off drain capacitance ?0.6 pc charge injection low leakage: 0.4 na maximum at 85c 9 v to 22 v dual-supply operation 9 v to 40 v single-supply operation 48 v supply maximum ratings fully specified at 15 v, 20 v, +12 v, and +36 v v ss to v dd analog signal range applications automatic test equipment data acquisition instrumentation avionics audio and video switching communication systems functional block diagram s 1 1 of 4 decoders adg5204 s 2 d s 3 s 4 a0 a1 en 09768-001 figure 1. general description the adg5204 is a complementary metal oxide semiconductor (cmos) analog multiplexer, comprising four single channels. the ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-and- hold applications, where low glitch and fast settling are required. fast switching speed together with high signal bandwidth make the adg5204 suitable for video signal switching. the adg5204 is designed on a trench process, which guards against latch-up. a dielectric trench separates the p and n channel transistors, thereby preventing latch-up even under severe overvoltage conditions. the adg5204 switches one of four inputs to a common output, d, as determined by the 3-bit binary address lines, a0, a1, and en. logic 0 on the en pin disables the device. each switch con- ducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. all switches exhibit break-before-make switching action. product highlights 1. trench isolation guards against latch-up. a dielectric trench separates the p and n channel transistors, thereby preventing latch-up even under severe overvoltage conditions. 2. ultralow capacitance and <1 pc charge injection. 3. dual-supply operation. for applications where the analog signal is bipolar, the adg5204 can be operated from dual supplies up to 22 v. 4. single-supply operation. for applications where the analog signal is unipolar, the adg5204 can be operated from a single rail power supply up to 40 v. 5. 3 v logic-compatible digital inputs. v inh = 2.0 v, v inl = 0.8 v. 6. no v l logic power supply required.
adg5204 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual supply ....................................................................... 4 12 v single supply........................................................................ 5 36 v single supply........................................................................ 6 continuous current per channel, sx or d ............................... 7 absolute maximum ratings ............................................................8 esd caution...................................................................................8 pin configurations and function descriptions ............................9 truth table .....................................................................................9 typical performance characteristics ........................................... 10 test circuits..................................................................................... 14 terminology .................................................................................... 16 trench isolation.............................................................................. 17 applications information .............................................................. 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 5/11revision 0: initial version
adg5204 rev. 0 | page 3 of 20 specifications 15 v dual supply v dd = 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v max on resistance, r on 160 typ v s = 10 v, i s = ?1 ma, see figure 24 200 250 280 max v dd = +13.5 v, v ss = ?13.5 v on-resistance match between channels, ?r on 4.5 typ v s = 10 v, i s = ?1 ma 8 9 10 max on-resistance flatness, r flat(on) 38 typ v s = 10 v, i s = ?1 ma 50 65 70 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off) 0.01 na typ v s = v s = 10 v, v d = ? 10 v, see figure 23 0.1 0.2 0.4 na max drain off leakage, i d (off) 0.01 na typ v s = v s = 10 v, v d = ? 10 v, see figure 23 0.1 0.4 1.2 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 10 v, see figure 26 0.2 0.5 1.2 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 175 ns typ r l = 300 , c l = 35 pf 230 285 320 ns max v s = 10 v, see figure 29 t on (en) 155 ns typ r l = 300 , c l = 35 pf 205 255 285 ns max v s = 10 v, see figure 31 t off (en) 150 ns typ r l = 300 , c l = 35 pf 175 200 215 ns max v s = 10 v, see figure 31 break-before-make time delay, t d 80 ns typ r l = 300 , c l = 35 pf 30 ns min v s1 = v s2 = 10 v, see figure 30 charge injection, q inj ?0.6 pc typ v s = 0 v, r s = 0 , c l = 1 nf, see figure 32 off isolation ?80 db typ r l = 50 , c l = 5 pf, f = 100 khz, see figure 25 channel-to-channel crosstalk ?80 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 28 ?3 db bandwidth 136 mhz typ r l = 50 , c l = 5 pf, see figure 27 insertion loss ?6.8 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 27 c s (off) 3 pf typ v s = 0 v, f = 1 mhz c d (off) 26 pf typ v s = 0 v, f = 1 mhz c d , c s (on) 30 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/max gnd = 0 v 1 guaranteed by design; not subject to production test.
adg5204 rev. 0 | page 4 of 20 20 v dual supply v dd = +20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v max on resistance, r on 140 typ v s = 15 v, i s = ?1 ma, see figure 24 160 200 230 max v dd = +18 v, v ss = ?18 v on-resistance match between channels, ?r on 4.5 typ v s = 15 v, i s = ?1 ma 8 9 10 max on-resistance flatness, r flat(on) 33 typ v s = 15 v, i s = ?1 ma 45 55 60 max leakage currents v dd = +22 v, v ss = ?22 v source off leakage, i s (off) 0.01 na typ v s = 15 v, v d = ? 15 v, see figure 23 0.1 0.2 0.4 na max drain off leakage, i d (off) 0.01 na typ v s = 15 v, v d = ? 15 v, see figure 23 0.1 0.4 1.2 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 15 v, see figure 26 0.2 0.5 1.2 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 160 ns typ r l = 300 , c l = 35 pf 215 260 290 ns max v s = 10 v, see figure 29 t on (en) 150 ns typ r l = 300 , c l = 35 pf 185 225 255 ns max v s = 10 v, see figure 31 t off (en) 150 ns typ r l = 300 , c l = 35 pf 175 195 210 ns max v s = 10 v, see figure 31 break-before-make time delay, t d 75 ns typ r l = 300 , c l = 35 pf 30 ns min v s1 = v s2 = 10 v, see figure 30 charge injection, q inj ?0.6 pc typ v s = 0 v, r s = 0 , c l = 1 nf, see figure 32 off isolation ?80 db typ r l = 50 , c l = 5 pf, f = 100 khz, see figure 25 channel-to-channel crosstalk ?80 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 28 ?3 db bandwidth 150 mhz typ r l = 50 , c l = 5 pf, see figure 27 insertion loss ?6 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 27 c s (off) 3 pf typ v s = 0 v, f = 1 mhz c d (off) 26 pf typ v s = 0 v, f = 1 mhz c d , c s (on) 30 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/max gnd = 0 v 1 guaranteed by design; not subject to production test.
adg5204 rev. 0 | page 5 of 20 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v max on resistance, r on 340 typ v s = 0 v to 10 v, i s = ?1 ma, see figure 24 500 610 700 max v dd = 10.8 v, v ss = 0 v on-resistance match between channels, ?r on 5 typ v s = 0 v to 10 v, i s = ?1 ma 20 21 22 max on-resistance flatness, r flat(on) 145 typ v s = 0 v to 10 v, i s = ?1 ma 280 335 370 max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off) 0.01 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 23 0.1 0.2 0.4 na max drain off leakage, i d (off) 0.01 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 23 0.1 0.4 1.2 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 1 v/10 v, see figure 26 0.2 0.5 1.2 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 240 ns typ r l = 300 , c l = 35 pf 350 445 515 ns max v s = 8 v, see figure 29 t on (en) 250 ns typ r l = 300 , c l = 35 pf 335 420 485 ns max v s = 8 v, see figure 31 t off (en) 160 ns typ r l = 300 , c l = 35 pf 195 220 240 ns max v s = 8 v, see figure 31 break-before-make time delay, t d 140 ns typ r l = 300 , c l = 35 pf 60 ns min v s1 = v s2 = 8 v, see figure 30 charge injection, q inj ?1.2 pc typ v s = 6 v, r s = 0 , c l = 1 nf, see figure 32 off isolation ?80 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 25 channel-to-channel crosstalk ?80 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 28 ?3 db bandwidth 106 mhz typ r l = 50 , c l = 5 pf, see figure 27 insertion loss ?11 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 27 c s (off) 3.5 pf typ v s = 6 v, f = 1 mhz c d (off) 29 pf typ v s = 6 v, f = 1 mhz c d , c s (on) 33 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 65 a max v dd 9/40 v min/max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test.
adg5204 rev. 0 | page 6 of 20 36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v max on resistance, r on 150 typ v s = 0 v to 30 v, i s = ?1 ma, see figure 24 170 215 245 max v dd = 32.4 v, v ss = 0 v on-resistance match between channels, ?r on 4.5 typ v s = 0 v to 30 v, i s = ?1 ma 8 9 10 max on-resistance flatness, r flat(on) 35 typ v s = 0 v to 30 v, i s = ?1 ma 50 60 65 max leakage currents v dd = 39.6 v, v ss = 0 v source off leakage, i s (off) 0.01 na typ v s = 1 v/30 v, v d = 30 v/1 v, see figure 23 0.1 0.2 0.4 na max drain off leakage, i d (off) 0.01 na typ v s = 1 v/30 v, v d = 30 v/1 v, see figure 23 0.1 0.4 1.2 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 1 v/30 v, see figure 26 0.2 0.5 1.2 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 180 ns typ r l = 300 , c l = 35 pf 250 275 305 ns max v s = 18 v, see figure 29 t on (en) 170 ns typ r l = 300 , c l = 35 pf 220 251 285 ns max v s = 18 v, see figure 31 t off (en) 170 ns typ r l = 300 , c l = 35 pf 210 215 220 ns max v s = 18 v, see figure 31 break-before-make time delay, t d 80 ns typ r l = 300 , c l = 35 pf 30 ns min v s1 = v s2 = 18 v, see figure 30 charge injection, q inj ?0.6 pc typ v s = 18 v, r s = 0 , c l = 1 nf, see figure 32 off isolation ?80 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 25 channel-to-channel crosstalk ?80 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 28 ?3 db bandwidth 136 mhz typ r l = 50 , c l = 5 pf, see figure 27 insertion loss ?6.7 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 27 c s (off) 3 pf typ v s = 18 v, f = 1 mhz c d (off) 26 pf typ v s = 18 v, f = 1 mhz c d , c s (on) 30 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 85 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9/40 v min/max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test.
adg5204 rev. 0 | page 7 of 20 continuous current per channel, sx or d table 5. parameter 25c 85c 125c unit continuous current, sx or d pins v dd = +15 v, v ss = ?15 v tssop ( ja = 112.6c/w) 24.5 7.5 2.8 ma max lfcsp ( ja = 30.4c/w) 35.7 7.7 2.8 ma max v dd = +20 v, v ss = ?20 v tssop ( ja = 112.6c/w) 26 7.5 2.8 ma max lfcsp ( ja = 30.4c/w) 37 7.7 2.8 ma max v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 18 7 2.8 ma max lfcsp ( ja = 30.4c/w) 28 7.7 2.8 ma max v dd = 36 v, v ss = 0 v tssop ( ja = 112.6c/w) 30 7.7 2.8 ma max lfcsp ( ja = 30.4c/w) 41 7.7 2.8 ma max
adg5204 rev. 0 | page 8 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. parameter rating v dd to v ss 48 v v dd to gnd ?0.3 v to +48 v v ss to gnd +0.3 v to ?48 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx or d pins 81 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, sx or d 2 data + 15% operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c thermal impedance, ja 16-lead tssop, ja thermal impedance (4-layer board) 112.6c/w 16-lead lfcsp, ja thermal impedance (4-layer board) 30.4c/w reflow soldering peak temperature, pb free 260(+0/?5)c only one absolute maximum rating can be applied at any one time. esd caution 1 overvoltages at the sx and d pins ar e clamped by internal diodes. limit current to the maximum ratings given. 2 see . table 5
adg5204 rev. 0 | page 9 of 20 pin configurations and function descriptions adg5204 nc = no connect 1 2 3 4 5 6 7 en v ss s1 nc d s2 a0 14 13 12 11 10 9 8 gnd v dd s3 nc nc s4 a1 top view (not to scale) 09768-002 figure 2. tssop pin configuration notes 1. nc = no connect. 2 . exposed pad tied to substrate, v ss . 1v ss 2 nc 3 s1 4 s2 11 v dd 12 gnd 10 s3 9s4 5 nc 6 d 7 nc 8 nc 15 a0 16 en 14 a1 13 nc top view (not to scale) adg5204 09768-003 figure 3. lfcsp pin configuration table 7. pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when this pin is low, the device is disabled and all switches are off. when this pin is high, the ax logi c inputs determine the on switches. 3 1 v ss most negative power supply potential. 4 3 s1 source terminal. can be an input or an output. 5 4 s2 source terminal. can be an input or an output. 6 6 d drain terminal. can be an input or an output. 7 to 9 2, 5, 7, 8, 13 nc no connect. these pins are open. 10 9 s4 source terminal. can be an input or an output. 11 10 s3 source terminal. can be an input or an output. 12 11 v dd most positive power supply potential. 13 12 gnd ground (0 v) reference. 14 14 a1 logic control input. n/a 1 ep exposed pad exposed pad. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . 1 n/a means not applicable. truth table table 8. en a1 a0 s1 s2 s3 s4 0 x 1 x 1 off off off off 1 0 0 on off off off 1 0 1 off on off off 1 1 0 off off on off 1 1 1 off off off on 1 x is dont care.
adg5204 rev. 0 | page 10 of 20 typical performance characteristics 160 0 20 40 60 80 100 120 140 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resistance ( ? ) v s , v d (v) t a = 25c v dd = +18v v ss = ?18v v dd = +20v v ss = ?20v v dd = +22v v ss = ?22v 09768-104 figure 4. r on as a function of v d or v s , dual supply 250 200 150 100 50 0 ?20 ?15 ?10 ?5 0 5 10 15 20 on resistance ( ? ) v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +13.2v v ss = ?13.2v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v 09768-105 figure 5. r on as a function of v d or v s , dual supply 500 450 400 350 300 250 200 150 100 50 0 01 4 12 10 8642 on resistance ( ? ) v s , v d (v) t a = 25c v dd = 9v v ss = 0v v dd = 10.8v v ss = 0v v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v 09768-106 figure 6. r on as a function of v d or v s , single supply 160 140 120 100 80 60 40 20 0 04 353025201510 5 on resistance ( ? ) v s , v d (v) 0 t a = 25c v dd = 32.4v v ss = 0v v dd = 36v v ss = 0v v dd = 39.6v v ss = 0v 09768-107 figure 7. r on as a function of v d or v s , single supply 250 200 150 100 50 0 ?15 ?10 ?5 0 5 10 15 on resistance ( ? ) v s, v d (v) v dd = +15v v ss = ?15v t a = +125c t a = +85c t a = +25c t a = ?40c 09768-108 figure 8. r on as a function of v d or v s , for different temperatures, 15 v dual supply 200 160 120 80 40 180 140 100 60 20 0 ?20 ?15 ?10 ?5 0 5 10 20 15 on resistance ( ? ) v s, v d (v) v dd = +20v v ss = ?20v t a = +125c t a = +85c t a = +25c t a = ?40c 09768-109 figure 9. r on as a function of v d or v s , for different temperatures, 20 v dual supply
adg5204 rev. 0 | page 11 of 20 500 400 300 200 100 450 340 250 150 50 0 024681012 on resistance ( ? ) v s, v d (v) v dd = 12v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09768-110 figure 10. r on as a function of v d or v s for different temperatures, 12 v single supply 250 200 100 150 50 0 03 5 30 25 20 15 10 5 on resistance ( ? ) v s, v d (v) v dd = 36v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09768-111 figure 11. r on as a function of v d or v s for different temperatures, 36 v single supply 10 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 20 40 60 80 100 120 leakage current (pa) temperature (c) v dd = +15v v ss = ?15v v bias = +10v/?10v i d (off) ? + i s (off) ? + i s (off) + ? i d (off) + ? i d, i s (on) + + i d, i s (on) ? ? 09768-112 figure 12. leakage current vs. temperature, 15 v dual supply 0 20 40 60 80 100 120 temperature (c) 100 ?200 ?150 ?100 ?50 0 50 leakage current (pa) v dd = +20v v ss = ?20v v bias = +15v/?15v i d (off) ? + i s (off) ? + i s (off) + ? i d (off) + ? i d, i s (on) + + i d, i s (on) ? ? 09768-113 figure 13. leakage current vs. temperature, 20 v dual supply 0 20406080100120 temperature (c) 40 20 ?120 ?100 ?80 ?60 ?40 ?20 0 leakage current (pa) v dd = 12v v ss = 0v v bias = 1v/10v i d (off) ? + i s (off) ? + i s (off) + ? i d (off) + ? i d, i s (on) + + i d, i s (on) ? ? 09768-114 figure 14. leakage current vs. temperature, 12 v single supply 0 20406080100120 temperature (c) 50 ?250 ?200 ?150 ?100 ?50 0 leakage current (pa) v dd = 36v v ss = 0v v bias = 1v/30v i d (off) ? + i s (off) ? + i s (off) + ? i d (off) + ? i d ,i s (on) + + i d ,i s (on) ? ? 09768-115 figure 15. leakage current vs. temperature, 36 v single supply
adg5204 rev. 0 | page 12 of 20 10k 100k 1m 10m 100m 1g frequency (hz) 0 ?120 ?100 ?80 ?60 ?40 ?20 off isolation (db) t a = 25c v dd = +15v v ss = ?15v 09768-116 figure 16. off isolation vs. frequency, 15 v dual supply 10k 100k 1m 10m 100m 1g frequency (hz) 0 ?120 ?100 ?80 ?60 ?40 ?20 crosstalk (db) t a = 25c v dd = +15v v ss = ?15v between s1 and s2 between s1 and s4 09768-117 figure 17. crosstalk vs. frequency, 15 v dual supply ?20 ?10 0 10 20 30 40 v s (v) 2.5 2.0 1.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 charge injection (pc) t a = 25c v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = +36v v ss = 0v v dd = +12v v ss = 0v 09768-119 figure 18. charge injection vs. source voltage 350 300 250 200 150 100 50 0 ?40 ?20 0 20 40 60 80 100 120 time (ns) temperature (c) v dd = +12v v ss = 0v v dd = +36v v ss = 0v v dd = +15v v ss = ?15v v dd = +20v v ss = ?20v 09768-120 figure 19. transition time vs. temperature 1k 10k 100k 1m 10m frequency (hz) 0 ?120 ?100 ?80 ?60 ?40 ?20 acpsrr (db) t a = 25c v dd = +15v v ss = ?15v no decoupling capacitors decoupling capacitors 09768-121 figure 20. acpsrr vs. frequency, 15 v dual supply ?15 ?10 ?5 0 5 10 15 v s (v) 0 5 10 15 40 35 30 25 20 capacitance (pf) t a = 25c v dd = +15v v ss = ?15v source/drain on drain off source off 09768-123 figure 21. capacitance vs. source voltage, dual supply
adg5204 rev. 0 | page 13 of 20 100k 1m 10m 100m 1g frequency (hz) 0 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 attenuation (db) t a = 25c v dd = +15v v ss = ?15v 09768-125 figure 22. bandwidth
adg5204 rev. 0 | page 14 of 20 test circuits v s v d sx d a a i s (off) i d (off) 09768-006 figure 23. off leakage i ds sx d v s v 09768-005 figure 24. on resistance v out 50 ? network analyzer r l 50 ? sx d v s v dd v ss 0.1f v dd 0.1f v ss gnd 50 ? off isolation = 20 log v out v s 09768-008 figure 25. off isolation sx d a v d i d (on) nc nc = no connect 09768-007 figure 26. on leakage v out 50? network analyzer r l 50? sx d v s v dd v ss 0.1f v dd 0.1f v ss gnd insertion loss = 20 log v out with switch v out without switch 09768-009 figure 27. bandwidth channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50 ? r l 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 09768-010 figure 28. channel-to-channel crosstalk
adg5204 rev. 0 | page 15 of 20 v dd v ss v dd v ss v in s1 d gnd c l 35pf r l 300? v out v out 50% 50% 90% 90% address drive (v in ) a0 a1 s4 s3 s2 v s1 v s4 en 2.4v 0v 3v t transition t transition 0.1f 0.1f 09768-012 figure 29. address to output switching times v dd v ss v dd v ss c l 35pf r l 300 ? address drive (v in ) v out v out v in s1 d gnd 300? a0 a1 s4 s3 s2 v s1 en 2.4v 0.1f 0.1f t d 80% 80% 0v 3v 09768-013 figure 30. break-before-make time delay, t d enable drive (v in ) s1 d gnd c l 35pf r l 300 ? a0 a1 s4 s3 s2 en 0.1f 0.1f v in 300? t off (en) t on (en) 50% 50% 0.9v out 0.1v out output 0v 3v v out 0v v dd v ss v dd v ss v s v out 09768-014 figure 31. enable-to-output switching delay sx d v s gnd r s sw off sw off sw on sw off sw off a2a1 en v dd v ss v dd decoder v ss v out v out v in v in ? v out c l 1nf q inj = c l ? v out 09768-015 figure 32. charge injection
adg5204 rev. 0 | page 16 of 20 terminology i dd the positive supply current. i ss the negative supply current. v d , v s the analog voltage on terminal d and terminal s. r on the ohmic resistance between terminal d and terminal s. r flat(on) flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. i s (off) the source leakage current with the switch off. i d (off) the drain leakage current with the switch off. i d , i s (on) the channel leakage current with the switch on. v inl the maximum input voltage for logic 0. v inh the minimum input voltage for logic 1. i inl , i inh the input current of the digital input. c s (off) the off switch source capacitance, which is measured with reference to ground. c d (off) the off switch drain capacitance, which is measured with reference to ground. c d (on), c s (on) the on switch capacitance, which is measured with reference to ground. c in the digital input capacitance. t transition the delay time between the 50% and 90% points of the digital input and switch-on condition when switching from one address state to another. t on (en) the delay between applying the digital control input and the output switching on. see figure 31 . t off (en) the delay between applying the digital control input and the output switching off. see figure 31 . charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. acpsrr (ac power supply rejection ratio) the ratio of the amplitude of signal on the output to the amplitude of the modulation. this is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pins to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p.
adg5204 rev. 0 | page 17 of 20 trench isolation in the adg5204, an insulating oxide layer (trench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. in junction isolation, the n and p wells of the pmos and nmos transistors form a diode that is reverse-biased under normal operation. however, during overvoltage conditions, this diode can become forward-biased. a silicon controlled rectifier (scr) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. by using trench isolation, this diode is removed, and the result is a latch-up proof switch. nmos pmos p well n well buried oxide layer handle wafer trench 09768-004 figure 33. trench isolation
adg5204 rev. 0 | page 18 of 20 applications information the adg52xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. the adg5204 high voltage multiplexer allows single-supply operation from 9 v to 40 v and dual-supply operation from 9 v to 22 v.
adg5204 rev. 0 | page 19 of 20 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 34. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters 2.70 2.60 sq 2.50 compliant to jedec standards mo-220-wggc. 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.45 0.40 0.35 s eating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-16-2010-c figure 35. 16-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-16-17) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg5204bruz ?40c to +125c 14-lead thin shrink small outline package [tssop] ru-14 adg5204bruz-rl7 ?40c to +125c 14-lead thin shrink small outline package [tssop] ru-14 ADG5204BCPZ-RL7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-17 1 z = rohs compliant part.
adg5204 rev. 0 | page 20 of 20 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09768-0-5/11(0)

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